1. Field of the Invention
The present invention relates generally to an apparatus and method for controlling the temperature on a computer chip containing CMOS devices by performing real time dynamic power compensation.
2. Discussion of Related Art
Complementary metal-oxide semiconductors (CMOS) technology is well known. CMOS devices employ integrated field-effect transistors in a complimentary symmetry arrangement, which simulates a "push/pull" operation because of the placement of opposing-polarity devices (i.e., p-channel and n-channel FETs). CMOS technology has a variety of advantages over other MOS devices, including lower power requirements, superior noise immunity, higher fanout, higher tolerance to power supply variations, and higher temperature range.
Computer chips containing CMOS devices include time verniers which requires precise timing accuracy. Dynamic power variation of digital circuitry is an important issue in designing analog functions utilizing CMOS devices. The dynamic power variation changes chip temperature and it gives significant drift to the analog signal. Specifically, timing or propagation delay can be seriously impaired by the dynamic power variation. Propagation delay is affected by three parameters: capacitive loading, supply voltage, and temperature. Propagation delay is a function of ambient temperature. The temperature dependence of CMOS is much simpler than with TTL. In CMOS devices the carrier mobility changes, thus increasing the impedance and hence the delay with temperature. Consequently, it is an essential goal for the design of chips with precise time delay utilizing CMOS devices to control chip temperature.
Previously, there were primarily two techniques for controlling the temperature on a CMOS chip. First was the use of techniques which utilized a process which was relatively insensitive to clock frequency variation, such as bipolar processes. A significant drawback of this type of approach was the inherent high power consumption. A second technique tried to maintain low temperature gradients from the silicon to ambient temperature. By limiting the temperature gradients the effects of on chip heating could be minimized. However, although such on chip heating was minimized, it was not eliminated. Traditionally, low temperature gradients were achieved by expensive packaging techniques or the utilization of water cooling systems. Both these techniques added additional cost to the system.